codice:
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 0, 24576, LPXO, 0, 0, 30720000, 800, VDD_RAW(800) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 800, VDD_RAW(800) },
{ 0, 122880, PLL_3, 5, 5, 61440000, 800, VDD_RAW(800) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 800, VDD_RAW(800) },
{ 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 800, VDD_RAW(800) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 800, VDD_RAW(800) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 800, VDD_RAW(800) },
{ 1, 544000, PLL_2, 3, 0, 122800000, 900, VDD_RAW(900), &pll2_tbl[0] },
{ 1, 600000, PLL_2, 3, 0, 122800000, 925, VDD_RAW(925), &pll2_tbl[1] },
/* AXI has MSMC1 implications. See above. */
{ 1, 768000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 806400, PLL_2, 3, 0, 192000000, 1025, VDD_RAW(1025), &pll2_tbl[2]},
/* AXI has MSMC1. End */
{ 1, 1024000, PLL_2, 3, 0, 192000000, 1100, VDD_RAW(1100), &pll2_tbl[3]},
{ 1, 1200000, PLL_2, 3, 0, 192000000, 1100, VDD_RAW(1100), &pll2_tbl[4]},
{ 1, 1305600, PLL_2, 3, 0, 192000000, 1200, VDD_RAW(1200), &pll2_tbl[5]},
{ 1, 1401600, PLL_2, 3, 0, 192000000, 1250, VDD_RAW(1250), &pll2_tbl[6]},
{ 1, 1516800, PLL_2, 3, 0, 192000000, 1300, VDD_RAW(1300), &pll2_tbl[7]},
{ 1, 1612800, PLL_2, 3, 0, 192000000, 1400, VDD_RAW(1400), &pll2_tbl[8]},
{ 1, 1708800, PLL_2, 3, 0, 192000000, 1400, VDD_RAW(1400), &pll2_tbl[9]},
{ 1, 1804800, PLL_2, 3, 0, 192000000, 1450, VDD_RAW(1450), &pll2_tbl[10]},
{ 1, 1920000, PLL_2, 3, 0, 192000000, 1500, VDD_RAW(1500), &pll2_tbl[11]},
{ 1, 2016000, PLL_2, 3, 0, 192000000, 1550, VDD_RAW(1550), &pll2_tbl[12]},
{ 0 }
};